MCU reverse engineering

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.[3]

Some FPGAs have analog features in addition to digital functions. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.[4][5] Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.[6] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

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Field Programmable Gate Array (FPGA): Technology, Security and Reverse Engineering Overview

1. History and Origin

The FPGA ecosystem evolved from early programmable semiconductor components including PROMs and PLDs, which supported both factory batch programming and field configuration. These early devices featured fixed hardwired gate interconnects, lacking the dynamic routing flexibility that defines modern FPGAs. To address the demand for large-scale reconfigurable hardware, the Naval Surface Warfare Department funded Steve Casselman’s project in the late 1980s to build a system with 600,000 reprogrammable gates, resulting in a patented architecture that laid the groundwork for modern large-density programmable logic. Core theories for logic arrays and block structures were defined in 1985 patents by David W. Page and LuVerne R. Peterson, forming the theoretical foundation of today’s programmable hardware design.

In 1985, Xilinx founders Ross Freeman and Bernard Vonderschmitt released the XC2064, the first commercially successful FPGA. Unlike prior PLDs, it featured fully programmable logic gates and flexible interconnects, marking the birth of the commercial FPGA market. The XC2064 contained only 64 configurable logic blocks with dual 3-input LUTs, a modest specification by modern standards. Freeman was later inducted into the National Inventors Hall of Fame for this groundbreaking achievement. Xilinx dominated the market until the mid-1990s, when competitors like Actel emerged and captured nearly 18 percent of the global market share.

The 1990s witnessed rapid advancement in FPGA complexity and production volume. Early in the decade, FPGAs were limited to telecommunications and networking infrastructure. By the late 1990s, improved density and cost efficiency expanded their usage into automotive, industrial, and consumer embedded systems. This widespread adoption was driven by shrinking process nodes, integrated DSP capabilities, and simplified board-level integration for embedded mcu and microcontroller co-design scenarios.

2. Modern Hybrid FPGA Architecture

A dominant modern trend integrates traditional FPGA logic fabric with embedded processor cores to create a system on a programmable chip. This concept originated in the 1982 Burroughs SB24 design, which combined reconfigurable CPU logic on a single die. Today’s commercial implementations include the Xilinx Zynq-7000 with a 1.0 GHz dual-core ARM Cortex-A9, the Altera Arria V with an 800 MHz dual-core ARM processor, and the Atmel FPSLIC pairing an AVR core with programmable logic. The Actel SmartFusion further integrates a Cortex-M3 core, embedded flash, RAM, and analog peripherals into flash-based FPGA fabric.

Launched in 2010, the Xilinx Zynq-7000 defined the All Programmable SoC category, merging hardened ARM microcontroller hardware with FPGA logic to lower development barriers for embedded engineers. Fabricated on a 28 nm process, it unifies serial software processing and parallel hardware acceleration, addressing the growing complexity of modern embedded designs. Monolithic integration reduces power consumption, minimizes PCB interconnections, lowers component costs, and boosts system reliability, as most electronic failures stem from board-level chip connections rather than internal die defects.

Designers may also implement soft processor cores such as MicroBlaze, Nios II, and Mico32 entirely within FPGA logic resources instead of using hardened macro cores. Contemporary FPGAs support runtime partial reconfiguration, enabling reconfigurable computing where hardware logic adapts dynamically to task requirements. Beyond traditional FPGAs, hybrid devices like the Stretch S5000 combine software-configurable processor arrays and FPGA-like logic on one die to deliver adaptive computing performance.

3. Density Growth, Market Scale and ASIC Comparison

FPGA gate density has grown exponentially across decades: 8,192 gates in the 1982 Burroughs platform, 9,000 gates in 1987 Xilinx devices, 600,000 gates in the 1992 naval prototype, and millions of gates by the early 2000s. The commercial market expanded from $14 million in 1987 to over $385 million in 1993, $1.9 billion in 2005, and a projected $2.75 billion in 2010. Global FPGA design starts rose from 80,000 in 2005 to 90,000 in 2008, reflecting rising industry adoption.

Historically, FPGAs lagged ASICs in speed, power efficiency and logic density, requiring 40 times the area, 12 times the dynamic power, and operating at one-third the speed of equivalent ASIC implementations. Modern families like Xilinx Virtex-7 and Altera Stratix have closed this gap, rivaling ASIC performance with lower material costs and on-the-fly reconfiguration. Complex designs once requiring 6–10 discrete ASICs can now be consolidated onto a single advanced FPGA.

FPGAs offer field reprogrammability to fix deployed firmware bugs, shorten time-to-market, and eliminate expensive non-recurring engineering fees. Many developers adopt a hybrid workflow, prototyping on FPGAs before taping out final ASICs for high-volume production. Xilinx identifies rising IC costs, lengthened ASIC development cycles, shrinking R&D resources, revenue risks from delayed launches, and economic cost constraints as key trends making FPGAs ideal for mid-to-high volume applications.

4. CPLD vs FPGA Core Differences

The distinction between CPLDs and FPGAs is primarily architectural. CPLDs use rigid sum-of-products logic arrays paired with limited clocked registers, delivering predictable timing delays and a high logic-to-interconnect ratio with limited design flexibility. FPGAs are routing-dominant, offering vastly greater design flexibility but more complex timing closure for developers. In practice, FPGAs provide far larger resource capacity and commonly embed multipliers, memory, and high-speed SERDES, features rarely seen in CPLDs.

A key hardware difference lies in non-volatile storage: most CPLDs integrate on-board flash to hold configuration data for instant power-on operation. Traditional SRAM-based FPGAs rely on external storage, making them vulnerable to read-out attacks during boot initialization, which links directly to reverse engineering and firmware extraction workflows targeting embedded microcontroller systems.

5. FPGA Security, Reverse Engineering and Hardware Attack Vectors

FPGA security presents unique tradeoffs compared to ASICs and secure microcontroller devices. Blank FPGA dice contain no fixed logic during manufacturing, lowering the risk of malicious hardware implantation during fabrication. However, traditional SRAM FPGAs expose their bitstream when loading from external flash, creating vulnerabilities that attackers exploit to dump flash contents and conduct unauthorized data retrieval. Modern vendors mitigate this with up to 256-bit AES bitstream encryption and authentication for external storage.

Flash-based FPGAs such as Microsemi ProAsic 3 and Lattice XP2 store configuration internally, eliminating external bitstream exposure without mandatory encryption. These devices also offer SEU radiation resistance for space applications, enhancing reliability in extreme environments. For locked commercial FPGA and mcu devices, security is enforced by dedicated lockbit registers and programmable hardware fuses that activate a global lock state to block unauthorized debug access and memory probing.

To unlock protected chips, adversaries deploy both non-invasive and physical techniques. Voltage glitching during boot-time fuse sampling can temporarily disable lockbit enforcement, allowing attackers to dump critical eeprom sectors that store device fingerprints and security metadata. For permanently locked chips with blown fuses, precise decapsulation removes the chip epoxy to expose the silicon die, enabling laser modification of one-time programmable fuses to permanently disable hardware security barriers.

After a successful dump of flash and eeprom data, engineers perform comprehensive firmware extraction to retrieve raw binary configuration files. The next stage is code recovery, where decompilation tools reconstruct human-readable HDL or pseudo-code from captured bitstream data. Through detailed reverse engineering, analysts decode hidden control logic, authentication mechanisms, and peripheral interaction routines embedded within the original design.

Recovered design data can be modified to remove anti-cloning restrictions, allowing threat actors to program the altered bitstream onto blank hardware and create an exact duplicate of the original locked device. This piracy risk threatens industrial intellectual property, especially for FPGA-based mcu control systems used in automotive and aerospace hardware. Ethical security researchers use the same techniques to identify lockbit weaknesses, optimize fuse configuration schemes, and strengthen native FPGA security against illegal duplication.

6. Applications, Architecture and Design Flow

FPGAs serve diverse fields including DSP, software-defined radio, ASIC prototyping, medical imaging, computer vision, cryptography, and industrial detection systems. Originally used as simple PCB glue logic to replace CPLDs, they now function as full SoCs after integrating dedicated multipliers in the late 1990s. Traditionally used for low-volume products due to programmable unit cost premiums, modern cost dynamics have expanded their use into high-volume consumer markets.

Key vertical applications cover aerospace DO-254 avionics, telecom baseband processing, automotive infotainment, broadcast video encoding, data center routing, HPC supercomputing, industrial motor control, and medical scanning equipment. Early cryptocurrency mining also leveraged FPGA parallel computing strengths before the shift to ASIC-based mining hardware.

Standard FPGA architecture consists of a grid of configurable logic blocks, peripheral I/O pads, and uniform routing channels. Logic cells typically include a LUT, full adder, and flip-flop; modern high-end devices adopt 6-input LUTs for improved efficiency. Dedicated global routing networks manage low-skew clock signals separately from general interconnect tracks. Routing segments terminate at switch boxes, which can be chained to form long-distance signal paths across the array.

Hardened embedded blocks including DSP multipliers, memory banks, and transceivers improve performance over logic-generated equivalents. FPGAs are critical for pre-silicon ASIC validation and firmware development, accelerating time-to-market for new chip products. Vendors including Xilinx and Tabula have developed 3D stacked-die FPGAs using silicon interposers to boost density without expanding package size.

The standard FPGA design flow uses VHDL or Verilog for design entry, followed by synthesis, place-and-route, timing analysis, and simulation to generate a configuration bitstream. The bitstream is loaded via JTAG or external memory. High-level tools like LabVIEW simplify programming, while pre-built IP cores accelerate development. Design teams conduct RTL, gate-level, and post-route timing simulation to verify functionality before deployment.

7. Process Technology and Manufacturers

FPGA process technologies include SRAM for unlimited reprogramming, one-time antifuse for maximum security, obsolete PROM/EPROM components, electrically reconfigurable EEPROM, density-optimized flash devices, and legacy bipolar fuse-based hardware. CMOS is the dominant transistor technology for all modern programmable logic products.

Xilinx and Intel Altera control over 80 percent of the global FPGA market, providing free design software for Windows and Linux platforms. Niche competitors include low-power specialist Lattice Semiconductor, secure aerospace-focused Microsemi, high-speed Achronix, and handheld-device oriented QuickLogic. Tabula’s 2010 time-multiplexed FPGA architecture offered density optimization through virtualized logic resource sharing.